(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method to enhance uniformity in thickness of created layers of native oxide.
(2) Description of the Prior Art
The functionality of semiconductor devices can be roughly divided into logic or data manipulation functions and storage or data retention functions. In the latter category fall Read Only Memory (ROM) devices also referred to as mask-programmed devices. ROM devices are non-volatile memories, data is permanently stored in the devices during the fabrication of the devices through the use of custom masks. A desired bit pattern of the memory retained in the ROM device, each bit pattern is provided for one particular application of the ROM device. Only read operations can be performed, changes of the data contained in the memory cannot be made after the device has been fabricated. Customization of the device is however economically feasible since only one mask needs to be used for the fabrication of the ROM device. ROM devices have been implemented using bipolar and CMOS technologies. A typical application of ROM devices is in the interface between central processors and other therewith connected data processing devices. The ROM devices are used for the elimination of system xe2x80x9cwaitxe2x80x9d states and hence to improve the operational speed of the data processing system.
Different data are stored in a ROM device by the presence or the absence of a conductive data path between a word line (the access path of the memory) to a bit line (the sense line of the memory). No data element will be provided if the word line and the bit line are not interconnected by a circuit element if therefore the word line of a ROM is activated, the presence of a signal on the bit line indicates that a xe2x80x9c1xe2x80x9d is stored in that data element (bit location). The absence of a signal on the bit line indicates that a xe2x80x9c0xe2x80x9d is stored in that bit location. The implementation of the ROM device uses either a complement of NOR function or a complement of NAND function. The imbedding of data in ROM devices (zero or one bit conditions) takes place by selectively omitting a contact.
Field-programmable ROM (PROM) devices are ROM devices that are typically manufactured in small quantities, these devices are programmed individually in order to save overall manufacturing costs. Some ROM devices are manufactured such that data, once entered into the device, cannot be erased. Other ROM devices allow the data to be erased and to be re-entered after the device has been manufactured. Initially, such devices have predominantly been created using bipolar technology, more recent developments use MOS technology for the creation of these devices. The Erasable PROM (EPROM) devices depend on the long-term retention of data, this data is retained as an electronic charge and is stored on a polysilicon gate of a MOS device. The term xe2x80x9cfloatingxe2x80x9d in this structure refers to the fact that no electrical connection exists to the gate that retains the electrical charge. The charge is therefore transferred from the silicon substrate through an insulator. In order for the charge to be erased, the stored charge must be erased from the floating gate. This erasure can be achieved by exposing the EPROM to UV light for a time of up to about 20 minutes. This UV light creates a discharge path for the floating gate. EPROM cells typically consist of only one transistor making it possible to create very high-density arrays of EPROM cells. The UV light that is used to erase EPROM cells however brings with it the requirement that EPROM cells must be packaged in relatively expensive ceramic packages that contain a UV-transparent window. The devices must also, during the process of erasure, be removed from their operating environment and placed in a special UV eraser. To counter these disadvantages, electrically erasable PROM""s (EEPROM""s) have been created. These EEPROM devices are implemented using either floating-gate tunnel oxide (FLOTOX) MOS devices or using textured-polysilicon floating-gate MOS devices. FLOTOX MOS devices consist of a MOS transistor with two poly gates, the textured-polysilicon floating-gate MOS devices consists of three partially overlapping layers of poly creating a cell that acts as three in series connected MOS devices. In this arrangement, the floating-gate MOS device is formed in the middle of the poly structure, this device is encapsulated in SiO2 in order to provide this device with high charge retention. The tunneling that is required to affect the charge transfer will, in this case, take place from one poly structure to another rather than from the substrate to the floating gate. Textured poly gates are programmed by causing electrons to flow (tunnel) from the floating poly structure to poly 3. A relatively high voltage is established on the poly 3 during both the programming and the erase operations. The drain voltage determines whether the tunneling occurs from poly 1 to the floating gate or from the floating gate to poly 3. The drain voltage therefore determines the final state of the memory cell.
Another EEPROM cell is the flash EEPROM wherein all the memory cells can be rapidly and electrically erased in one operation. This operation of memory erasure can be performed on the entire memory array or on selected parts of the memory array, down to the erasure of individual bytes within the memory array. The erasing mechanism of the flash EEPROM consists of tunneling off the region between the floating gate and the drain region of the MOS device. Programming the flash EEPROM is carried out by hot carrier injection into the gate of the MOS device. Flash EEPROM typically will use the erasure of relatively large regions of memory, the floating gate EEPROM""s typically incorporate a separate select transistor, allowing for the erasure of individual bytes.
Most flash memory EEPROM devices use a double poly structure whereby the upper poly forms the control gate and the word lines of the structure while the lower poly is the floating gate. In a typical structure, the control-gate poly overlaps the channel region that is adjacent to the channel under the floating gate. The extension of the control gate over the channel region is referred to as the series enhancement-mode transistor and is required because when the cell is erased, a positive charge remains on the floating gate inverting the channel under floating gate. The series enhancement-mode transistor prevents the flow of current from the source to the drain regions of the MOS device.
For the simultaneous creation of flash memory devices in large quantities, it is of critical importance that the various elements that are comprised in the device are created in a uniform and identical manner. Specifically, the thickness of layers within the created device, such as a layer of native oxide that forms an interface between overlying layers of polysilicon, must be created within very close tolerances. The invention addresses the concern of creating a layer of native oxide of uniform thickness for batch produced flash memory devices.
U.S. Pat. No. 6,284,596 B1 (Sung et al.) shows a process for a floating gate and nitride layer.
U.S. Pat. No. 6,261,905 (Chen et al.) shows a flash memory process with a stacking gate formed by a damascene-like structure.
U.S. Pat. No. 6,242,308 B1 (Hsieh et al.) and U.S. Pat. No. 6,225,162 (Lin et al.) are related memory gate processes.
A principle objective of the invention is to enhance uniformity in thickness of created layers of native oxide.
Another objective of the invention is to remove the impact of the advancement of the processed substrate through a processing furnace on the thickness of a created layer of native oxide for a flash memory device.
Yet another objective of the invention is to improve uniformity of thickness of a deposited layer of native oxide for a flash memory device by making this deposition independent of the location or zone within a processing furnace.
A layer of gate oxide is created over the surface of a substrate, a layer of gate material is deposited over the surface of the layer of gate oxide. In a first embodiment of the invention, a layer of native oxide is grown over the surface of the layer of gate material, this layer of native oxide is used to enhance oxidation of exposed portions of the layer of gate material. In a second embodiment of the invention, enhanced oxidation of exposed portions of the layer of gate material is achieved by modifying the conventional sequence of the oxidation process. This latter modification is realized by modifying the forward motion of the substrates through the oxidation furnace or by modifying the sequence in which the substrates move through the oxidation furnace.